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Cache coherence
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31	Design of Parallel and High Performance Computing HS 2013 Markus P¨ uschel, Torsten Hoefler Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-09-26 05:52:30 Cache coherency MESI protocol Cache coherence Cache False sharing Multiprocessing Draft:Cache memory CPU cache
32	Review of last lecture  Cache-coherence is not enough!  Many more subtle issues for parallel programs! Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-10-13 13:49:30 Concurrency control Linearizability Lock Resource Acquisition Is Initialization FIFO Mutual exclusion Queue Monitor
33	Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-11-03 08:27:59 Computer memory Transaction processing Parallel computing Compiler construction Concurrency Cache coherence Memory ordering Consistency model Linearizability Sequential consistency CPU cache Processor consistency
34	Design of Parallel and High Performance Computing HS 2013 Markus P¨ uschel, Torsten Hoefler Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-10-10 09:58:44 Cache coherency MESI protocol Cache coherence Cache False sharing Draft:Cache memory CPU cache
35	A Case for Cache Coherence Ike Antkare International Institute of Technology United Slates of Earth A BSTRACT Add to Reading List Source URL: membres-lig.imag.fr Language: English - Date: 2014-01-09 04:24:28 Monte Carlo software Stan Ike Dwight D. Eisenhower
36	Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-10-04 17:36:16 Computer memory Transaction processing Computer architecture Concurrency control Compiler construction Memory ordering Consistency model Cache coherence Memory barrier Linearizability Schedule Sequential consistency
37	Cache Line Aware Optimizations for ccNUMA Systems Sabela Ramos Torsten Hoefler Computer Architecture Group Add to Reading List Source URL: htor.inf.ethz.ch Language: English - Date: 2015-04-13 08:17:39 Parallel computing Non-uniform memory access Nehalem Intel QuickPath Interconnect Xeon Cache coherence Multi-core processor Thread OpenMP Cache CPU cache Draft:Cache memory
38	Memory Coherence in Shared Virtual Memory Systems 1 Kai Li and Paul Hudak Department of Computer Science Yale University New Haven, CT 06520 Add to Reading List Source URL: css.csail.mit.edu Language: English - Date: 2014-12-08 14:33:01 Concurrent computing Computing Parallel computing Memory management Computer architecture Virtual memory Central processing unit Page Paging Draft:Cache memory Parallel random-access machine
39	A Mechanism to Verify Cache Coherence Transactions in Multicore Systems Rance Rodrigues, Israel Koren and Sandip Kundu Department of Electrical and Computer Engineering University of Massachusetts, Amherst MA 01003, USA. Add to Reading List Source URL: euler.ecs.umass.edu Language: English - Date: 2014-03-31 15:04:26
40	Themis: Enforcing Titanium Consistency on the NOW Carleton Miyamoto and Ben Liblit CS262 Semester Project Report Computer Science Division University of California at Berkeley {miyamoto,liblit}@CS.Berkeley.EDU Add to Reading List Source URL: titanium.cs.berkeley.edu Language: English - Date: 2014-04-29 06:11:57 Computing Cache coherency Computer architecture Concurrent computing Cache coherence Consistency model Cache memory Cache Sequential consistency MESI protocol Dragon write-back update protocol